Basic PCB Design Points
| Topic | Key Points |
|---|---|
| Basic Cost Factors | Material Selection, Layer Count, Panel Utilization, Hole Density per Square Inch, Technology Level, Quantity Releases & Competition Pricing |
| Density Characteristics | Density- Based on layer count, line width & spacing, SMD pitch, aspect ratio and number of holes per square inch. |
| Material Selection | Selection considerations: Operating temperature, soldering temperature, frequency of soldering operations & reliability. The major difference between the various types of material is the dielectric constant and the Tg. |
| Material CTE | CTE- Coefficients of Thermal Expansion. The glass fabric expands very little, copper will expand to a greater degree that the fabric and the epoxy with expand 4xs more than the fabric. In the X & Y axis the fabric will restrict growth, but not so in the Z-axis. |
| Copper Foil | The copper foil type is “electrodeposited” by electroplating copper to a very large and very smooth drum in a large electroplating tank. The drum side (smooth side) is up so as to better produce fine line traces. |
| Reinforcing Material | The reinforcing material is used as a base to hold the resins and give the boards stability. Some material types are paper, linen or woven glass. There are different types of woven glass fabric, but most common is the E-Glass. |
| Glass Styles | A glass style number designates the diameter of the glass strands relative to the weave. The lower the number the thinner the glass fabric. |
| Material Dielectric Constant | The ratio of glass to resin content in the core material and pre-preg will affect the dielectric constant (Er) considerably. The greater amount of resin the lower the Er. The lower Er allows for the faster a signal will propagate along a transmission line and the lower the propagation delay. |
| High Speed Signals | The component segment of the electronic industry has made great advances in component speed and density. This places a burden the on board fabricator, laminate supplier & mfg. of digital equipment to meet these new challenges. The most important design technique for high-speed signals is controlled impedance. |
| Impedance | The principle purpose of controlled impedance is to eliminate or minimize reflections from the end of the lines, and minimize discontinuities in the line. Reflections and discontinuities cause noise and signal ringing, which could cause malfunctioning of the circuitry if too sever. |
| Transmission Lines | An ideal transmission line will transport energy at high speeds from drivers to receivers with little loss in signal shape, magnitude or speed. A transmission line is defined as a line trace, a copper reference plan and a dielectric material. There are several types of transmission lines; microstrip, embedded microstrip, centered stripline and dual stripline. |
| Crosstalk | The best way to reduce noise between two adjacent layers is to separate them as much as possible. Also, the closer the signal traces run to the reference plane, the more the crosstalk is reduced. The quietest signal layers will be those that are sandwiched between two reference layers. |
| Warpage | Symmetrical- Layers & dielectric are symmetrical from center of board out Uniform Copper Areas- Areas void of copper causes low pressure points during lamination, which can result in warpage |
| Thickness | During the during lamination process the resins will flow (fill) around the traces and out to the edges creating a condition known as “loss to fill”. Various copper weights will result in different values for the loss to fill. The loss to fill is roughly 1/2 of the copper weight on signal layers, and 1/3 on plane layers. |
| Scaling | Inner layers will shrink during lamination but will shrink more in one direction than the other. The material will shrink more in the long direction (“warp”) of the roll than the shorter direction (“fill”). |
| Thin Cores | To make cores more rigid, add copper to all vacant areas over the entire core surface and make it look as much like a ground plane as possible. |
| Thieving | Outer layers: Along panel edges that acts like a “robber” for plating currents and within the board area (internal) to minimize high current density areas Inner layers: For thickness requirements, warpage control & rigidity of thin cores |
| Inner Layer Thieving/ Resin Flow | The thieving keeps the plane of material uniform and level. During lamination, the resins flow and has a tendency to become “frosted” or crystallized as they approach the outside edges of the panel. Therefore, the test coupons should be placed inward beyond the one-inch minimum border so as to avoid being in the crystallized area. It is best to remove non-functional pads as the pads without traces are less restricted and may “float” when the epoxy is flowing prior to cure. |
| Thermal Reliefs | Outer Layers- During the soldering operation, the solid copper plane will lift from the board surface. If the plated holes are not relieved, the corner of the hole will barrel crack. When the holes are relieved, the solid shield is allowed to lift independently from the land. Inner Layers- With a thermal relief, the X & Y axis expansion of the material is localized around the hole and not influenced by the entire plane. If there is no solder relief, the solder will not wick up all the way up of the barrel. (The assembler should NOT touch up these holes as it can cause damage to the holes and the board). |
| Edge Clearance | Plane layers and features should not extend any closer to the machined board edge than .050”. This ensures good lamination with no separation. |
| 90 degree corners | 90 degree trace bends may cause problems with etching and controlled impedance. Etching: During normal etching process the trace is attached from both sides. When etching the corner, the trace is attacked from three sides, the 3rd side being the extreme corner. With very slight over etching there maybe reliable issues especially on fine lines. Impedance: There will be slight reflection or bounce when the signal reaches the corner of the trace. This can be minimized with 45 degree angles. |
| Copper Plating Holes Shut | It is best not to have the copper plate the small holes shut as the corners plate the fastest leaving an area for solution entrapment. Later, the solution may leach out onto the board surface causing failures. |
| Wire Bonding | Gold thickness for aluminum wedge bonding is 5-15 mi. The nickel hardness is very important. Gold thickness for gold wire thermal bonding is 50 mi min. |
| Plating Quality | Plated copper in the hole will be more brittle than the plated copper on the surface. The corners of the holes (knees) are high current density areas, therefore, the more brittle the copper at the knees. Also, as the hole aspect ratio increases, the ductility problem increases. Therefore, when evaluating a cross section, check for barrel cracking of the copper. |
| Wetting | For a reliable solder connection, there must be wetting of solder to the copper surface on the board and wetting with the component lead. “Wetting” occurs when the solder reaches a high enough temperature to cause metallurgical alloying of copper and tin atoms at the interface of the copper and tin/lead surface. The rule of thumb temperature for wetting is 75 – 100 degrees higher than the melting temperature of the specific alloy being used. For eutectic solder (63/37) the range is between 435 – 460 degrees Fahrenheit. |
| Solderability | When hot air solder leveling, an intermetallic was formed between the copper and the tin. The tin was “stolen” from the solder, which affects the tin-lead ratio leaving more lead. The more times the board is subjected to soldering operations, the more remaining lead which causes the solderability to be degraded. |
| Ionic Contamination | The contamination may cause cross talk between traces and may also grow shorts when the humidity goes above 96%. |
| Dry Film SM | Due to the thickness of dry film mask, it is not recommended for SMD designs as it makes the solder paste application very difficult. The “well” around the SM lands allowed tombstoning of the components during placement. |
| SM Via Plugging | For hole plugging an epoxy thermal setting solder mask is used. The holes are plugged on the bottom side of the board and then both sides of the board are covered with LPI mask. The concern is that the LPI mask will not cover all of the bare copper in the hole. To be assured of no exposed copper, hole plugging should then be done after HASL, not before. |
Key Points from Bare Board PWB Design Manual
By Norman S. Einarson