Simulation

High Speed Capabilities

The following is a department-by-department synopsis of the tools and procedures specifically employed to address high frequency circuits

High Speed Simulation

R&D employs a staff of two full time microwave engineers, utilizing the latest Ansoft software for true 3d circuit simulation and optimization. This includes 3D modeling, 3D meshing, full wave finite element analysis, 3D post processing/ field visualization, planar 3D electromagnetic simulation, integrated schematic & layout capability, DXF, Gerber and GDSII importing and optometric.

Cam / Engineering

Polar impedance calculators and stack-up generator, for surface microstrip, coated microstrip, embedded micro strip, symmetrical stripline, offset stripline, edge-coupled surface micro strip, edge-coupled coated micro strip, edge-coupled embedded micro strip, edge coupled symmetrical stripline, edge coupled offset stripline, broad-side coupled stripline, surface coplanar line, coated coplanar line, embedded coplanar line, offset coplanar stripline and more….

Imaging

Collimated light source for superior line definition. Liquid electrophoritic photo resist , .0002” thick for true 1:1 transmission signal reproduction with straight side walls.

Etching

Ultra fine line etcher with computer controlled ball valves on each nozzle for pattern dependent etching and straight sidewalls.

Lamination

High temperature 800 deg. F lamination presses for Teflon fusion bonding, and many high performance high speed materials which require between the traditional 400 deg. F and the high temperature 800 deg. F now being installed at R&D.

Periodic Reverse pulse plating

Electrolytic copper plating for pattern and panel plating which pulses the current accentuating the high current density areas. Then periodically reverses the pulsed current flow removing copper ions from the high current density areas effectively leveling the copper across the board plane. This creates an extremely consistent etch rate across the panel and provides for much greater impedance control.

Coaxial PCB traces

R&D has developed a patent pending process by which a printed pcb traces can be totally encapsulated by ground plane on all four sides providing a true coaxial transmition line. Multiple layers of these coaxial lines can by designed into a multi layer printed circuit board utilizing an wide array of materials. This technology is ideally suited for 10 gig and beyond, high-speed back planes.

Lanless via technology

R&D has developed a new technology, which allows traces to be routed to vias without the associated pads. This greatly reduces the parasitic capacitance associated with through vias, and when combined with blind micro vias greatly reduces the inductance associated with the stub of a traditional through via.

High voltage testing

One hundred percent net list testing is provided on all R&D boards referencing your layout net list. This test performs opens testing with a selectable threshold from 1 Ohm to 1 kOhm, and a short testing is performed with a selectable threshold from .5 mOhm to 10 mOhm. Also, voltage can be selected from 50 volts to 500 volts.