Build Up Stacked ViaWhen routing density is so extreme, as in a .25 mm pitch BGA Design, even a staggered via build up simply won’t work. In such cases, it is necessary to incorporate a stacked via approach. As illustrated in the photo below, vias are stacked one on top of another as to achieve the highest possible routing density.To take advantage of this stacked via approach, we start with our center core, in this case layers 2 & 3. We then form our laser vias in core 2 & 3, utilizing (in this example) a .0035" laser via through .008" RO4003 core, as seen in this cross section below. We then register a .007" capture pad to the .0035" hole. This only allows for a .002" annular ring - therefore registration must be near perfect. We now plate copper in only the holes, and not on the surface foil. We accomplish this by utilizing a special process which allows us to only plate copper in the via, and not on the surface foil. This helps ensure minimum undercut during the etching process and consistent etched feature dimensions. However, before we etch the patterns on layers 3&4, we must fill the plated hole with "silver epoxy". This is done with a pressurized vessel, which forces the paste through the hole in one continuous motion. This process greatly reduces the occurence of air inclusions. The panels are then baked to cure the paste. At this point, the silver is precisely ground to planarize the paste to the surface of the board. Once this has been accomplished, we go back to the imaging department where a plating resist is applied and the patterns for layers 3&4 are imaged. We now plate copper onto the exposed pattern of layers 3&4. This copper plating is formed over the entire circuit image traces, pads, and over the planarized silver paste - forming a copper-to-copper connection from top of the core to the bottom of the core. It is important to note we are not relying on the silver paste to carry current. We are now ready to laminate on the next two layers, layers 1 & 4. In the project illustrated below we utilized .0022 Speed Board C material (a low Dk material suitable to 40 gig). Just about any prepreg or bonding material is available; please speak to your sales engineer for recommendations most suitable for your project. We are now ready to form our laser holes from layers 1 & 2 and 4 & 3. You will note on the photo below that a .0035" hole has been ablated through the .0025 dielectric between 1 & 2 and 4 & 3. You will also note that the holes needed to be registered to .007" pads on layers 2 &3. This only allows for .0025" misregistration across an 18 x24 panel. (.00225" annular ring). To maintain this registration our laser system skives away material from the top layers exposing fiducials etched onto all four corners of each internal layer below. The lasers vision system then aquires the targets and perform a best fit algorithm in order to scale the drill file in register to the pads below. This scaling compensates for any movement induced by previous processing. Once the laser holes have been formed we can then plate copper in the holes. For this particular example a .25 mm fill chip on top and a .5 mm BGA on the bottom it was necessary to fill the outer layer vias and turn them into BGA surface mount pads. The same silver filling process as described in the steps for filling the 2 & 3 core holes is utilized for both top and bottom blind vias. The outer vias are then plated over and the patterns are etched as previously described. As illustrated above, a .007" pad was used to maintain registration to the .0025 holes. However, a .0035" opening in the solder mask is necessary for the flip chip operation, which is in a 1:1 ratio to the pad on the chip. This is critical to maintain a consistent solder column height. However, this only provides for a .00175 annular ring from solder mask anti pad to copper pad. Any misregistration outside that tolerance results in a bad board, which makes the solder mask registration critical. This registration is accomplished much like the registration when imaging the copper features. However, instead of acquiring four fiducials from around the four corners of the panel in this case it was necessary to acquire four fiducials around 2 X 2 array of boards. The result of the project illustrated in the previous photos was a .25mm to .5mm - flipchip to BGA interposer chip carrier. This technology can also be applied to large format boards as in ATE type boards over 20" X 26". *Please ask one of our sales engineers to explain how to incorporate this technology into your next design. |
Top View of Array Stack Cross Section     Panel with 4 Skived Targets Silver Filled Bind  |
